In microchip fabrication, integrated circuits are formed on a semiconducting substrate. In general, various materials which are either conductive, insulating, or semiconducting are utilized to form the integrated circuits. These materials are patterned, doped with impurities, and deposited by various processes to form the integrated circuits. Active devices (e.g. transistors, diodes, etc.) formed on the substrate are interconnected utilizing metal lines embedded in a dielectric layer.
As silicon technology advances to ultra large scale integration (ULSI), the devices on silicon wafers shrink to sub-micron dimension and the circuit density increases to several million transistors per die. In order to accomplish this high device packing density, smaller and smaller feature sizes are required. This may include the geometry of various features and the width and spacing of the interconnecting lines.
These diminishing geometries have necessitated improved deposition and patterning techniques during the manufacture of semiconductor devices. As an example, dielectric layers formed over interlevel conducting lines are typically planarized to minimize topographic effects on subsequent photolithography processes. In a typical process, a dielectric layer is conformally deposited over patterned metal or semiconductor lines in such a way as to fill in the gaps between the lines. The dielectric deposition is followed by a planarization step such as chemical mechanical planarization (CMP), to remove excess material and planarize the surface topography.
In general, the chemical mechanical planarization (CMP) process involves holding a semiconductor substrate, such as a wafer, against a rotating wetted polishing pad under a controlled downward pressure. A polishing slurry, metered onto the polishing pad contains etchants and an abrasive material such as alumina or silica. A rotating polishing head or wafer carrier is typically utilized to hold the wafer under controlled pressure against the rotating polishing pad. The polishing pad is typically formed of a relatively soft wetted pad material such as a felt fiber fabric impregnated with blown polyurethane.
As patterned line widths become smaller, a conventional CMP process may not be entirely suitable for planarizing a dielectric layer of a semiconductor structure. As an example, the conformal deposition of a dielectric layer may not completely fill the gaps between conducting lines of a semiconductor structure. This may cause voids to be present in the completed dielectric layer. This situation is illustrated in FIGS. 1A and 1B.
With reference to FIG. 1A, a semiconductor structure includes a substrate 10 and an arrangement of patterned conducting lines 12. A dielectric layer 14 is being conformally deposited over the conducting lines 12 and into the gaps 16 between the conducting lines 12. As the deposition process is not perfectly conformal, however, the dielectric layer 14 bulges outwardly in the area 18 directly over the conducting lines. This phenomena is known as "breadloafing" or "cusping". The cusping effectively closes the mouth of the gaps 16 and increases the aspect ratio (depth/width) of the gaps 16. This makes filling of the gap with subsequently deposited dielectric material difficult. As the deposition process continues further, and as shown in FIG. 1B, voids 20 are formed in the dielectric layer 14.
These voids 20 are at a minimum, a cosmetic imperfection, which are not removed by the subsequent planarization process. More seriously, these voids 20 may be opened up during a subsequent planarization process (e.g. CMP) and adversely affect subsequent processing by outgassing or causing photo-notching during photopatterning of the dielectric layer 14. Furthermore, even if the voids 20 are not opened during planarization, outgassing from the voids 20 over extended periods of time may degrade the long term reliability of the semiconductor structure.
In order to prevent the formation of voids in a dielectric layer, improved dielectric materials and deposition processes have recently been developed for semiconductor manufacture. In general, such improved deposition processes and materials allow a more conformal deposition of high quality dielectric layers so that cusping or breadloafing of the dielectric material over the conducting liner is minimized. As an example, ozone doped tetraethyl orthosilicate based (TEOS) dielectric films can be deposited with a high degree of conformality utilizing new gas chemistries. These new deposition processes however, have not entirely eliminated the formation of voids.
Multistep deposition processes have also been developed to provide a more conformal deposition of a dielectric layer. As an example, an initial deposition of a dielectric layer is sometimes followed by an etch step and then by a second deposition step. The purpose of the etch step is to shape the profile of the initially deposited dielectric layer in such a way that no voids will form as the deposition process is continued. Such an etch step is sometimes referred to as "facet etch" because facet-like surfaces are formed in the etched material.
FIGS. 2A-2C illustrate such a multi step deposition process. With reference to FIG. 2A, a dielectric layer 14 (e.g. 3000-5000 angstroms) is again being deposited over parallel spaced conducting lines 12 and into the gaps 16 of a semiconductor structure. Instead of continuing the deposition process, however, the deposition procedure is stopped before the gaps are completely filled and the dielectric layer 14 is etched using a facet etch procedure. This is shown in FIG. 2B. The facet etch step can be performed using a anisotropic chemical etch or a physical sputter etch.
As shown in FIG. 2B, the facet etch step removes the breadloaf area 18 (FIG. 2A) of the dielectric layer 14. In addition, the facet etch step removes some of the dielectric layer 14 on the sidewalls of the conducting lines such that the mouth of the gaps 16 is opened and the width "w" of the gaps 16 is increased. The aspect ratio (depth/width) of the gaps 16 is thus decreased. In addition, the facet etch step shapes and facets the profile of the dielectric layer 14 and removes the corners of the breadloaf area 18 (FIG. 2A) substantially as shown in FIG. 2B.
Following the facet etch step, the deposition process is continued to complete the dielectric layer 14. As shown in FIG. 2C, however, voids 20 may still form within the dielectric layer 14. As with the prior art single step deposition process, with the present state of facet etch technology, complete void removal is not possible in one step. A series of deposition/etch steps are thus required to completely remove the voids. This is a limitation of a prior art multistep deposition/etch/deposition process. In addition, such multistep processes are relatively expensive and time consuming and require additional process equipment (e.g. vacuum etching equipment).
As is apparent then, there is a need in the art for an improved method for forming dielectric layers without the inclusion of voids. More generally, there is a need in the art for improved methods for shaping the features of a semiconductor structure that can be accomplished without etching.
Accordingly, it is an object of the present invention to provide an improved method for shaping the features of a semiconductor structure. It is yet another object of the present invention to provide an improved method for forming a dielectric layer of a semiconductor structure without the inclusion of voids. It is yet another object of the present invention to provide an improved method for shaping the features of a semiconductor structure using chemical mechanical planarization (CMP), that is efficient, cost effective, and adaptable to large scale semiconductor manufacture.